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ICS9LPRS436C idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 low power clock for intel atom ? -based systems datasheet 1 recommended application: nm10 express chipset + n450/d410/d510 atom ? cpus output features: ? 2 - 0.8v push-pull differential cpu pairs ? 2 - 0.8v push-pull differential pciex pairs ? 1 - 0.8v push-pull differential sata75 pair ? 1 - 0.8v push-pull differential dot96 pair ? 1 - 0.8v push-pull differential cpu/pciex selectable pair ? 1 - pci (33mhz) ? 1 - pciclk_f, (33mhz) free-running ? 1 - usb, 48mhz ? 1 - 12/48mhz ? 1 - 25mhz ? 1 - ref, 14.318mhz ? 1 - 12.288mhz key specifications: ? cpu outputs cycle-cycle jitter < 85ps ? pciex outputs cycle-cycle jitter < 125ps ? sata outputs cycle-cycle jitter < 125ps ? pci outputs cycle-cycle jitter < 500ps ? +/- 100ppm frequency accuracy on all clocks features/benefits: ? vddsusp allows 25mhz to run in s-states ? supports programmable spread percentage ? uses external 25mhz crystal, external crystal load caps are required for frequency tuning ? pereq# pins to support pciex/sata power management. ? low power differential clock outputs (no 50 resistor to gnd needed) ? integrated 33 series resistor on all differential outputs. pin configuration **fs3/12_288m_2x 148 gnd vdd12_288 247 gnd pereq1# 346 ref0_2x/fslc pereq2# 445 vdd14 **fs4/pciclk0_2x 544 vtt_pwrgd/wol_stop# gnd 643 vddsusp vddpci 742 25mhz **itp_en/pciclk_f0_2x 841 gnd pereq3# 940 x1_25 *sel12_48#/12_48mhz_2x 10 39 x2_25 vdd 11 38 pci&pciex_stop# fs l a/usb48_2x 12 37 cpu_stop# gnd 13 36 sdata dott_96mhzlr 14 35 sclk dotc_96mhzlr 15 34 gnd fs l b 16 33 cput_lr0 gndsata 17 32 cpuc_lr0 satat_lr/pciet_lr3 18 31 vddcpu satac_lr/pciec_lr3 19 30 cput_lr1 vddsata 20 29 cpuc_lr1 pciet_lr0 21 28 cpuitpt_lr2/pciet_lr2 pciec_lr0 22 27 cpuitpc_lr2/pciec_lr2 pciet_lr1 23 26 vddpciex pciec_lr1 24 25 gnd 48-tssop * internal pull-up resistor ** internal pull-down resistor 9lprs436 free datasheet http:///
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 2 gnd gnd ref0_2x/fslc vdd14 vtt_pwrgd/wol_stop# vddsusp 25mhz gnd x1_25 x2_25 pci&pciex_stop# cpu_stop# 48 47 46 45 44 43 42 41 40 39 38 37 **fs3/12_288m_2x 136 sdata vdd12_288 235 sclk pereq1# 334 gnd pereq2# 433 cput_lr0 **fs4/pciclk0_2x 532 cpuc_lr0 gnd 631 vddcpu vddpci 730 cput_lr1 **itp_en/pciclk_f0_2x 829 cpuc_lr1 pereq3# 928 cpuitpt_lr2/pciet_lr2 *sel12_48#/12_48mhz_2x 10 27 cpuitpc_lr2/pciec_lr2 vdd 11 26 vddpciex fsla/usb48_2x 12 25 gnd 13 14 15 16 17 18 19 20 21 22 23 24 gnd dott_96mhzlr dotc_96mhzlr fslb gndsata satat_lr/pciet_lr3 satac_lr/pciec_lr3 vddsata pciet_lr0 pciec_lr0 pciet_lr1 pciec_lr1 * internal pull-up resistor ** internal pull-down resistor 9lprs436 48 mlf 6x6mm 0.4mm pitch
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 3 pin description pin # pin name type description 1 **fs3/12_288m_2x i/o fre q uenc y select latch in p ut p in / 12.288mhz out p ut, 3.3v 2 vdd12_288 pwr power for 12.288mhz pll and out p ut buffer, nominal 3.3v. 3pereq1# in real-time input pin that controls sataclk and pciexclk outputs that are selected through the smbus. 1 = selected outputs are disabled, 0 = selected out p uts are enabled. 4pereq2# in real-time input pin that controls sataclk and pciexclk outputs that are selected through the smbus. 1 = selected outputs are disabled, 0 = selected out p uts are enabled. 5 **fs4/pciclk0_2x i/o fre q uenc y select latch in p ut p in / 3.3v pci clock out p ut. 6 gnd pwr ground p in. 7 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 8 **itp_en/pciclk_f0_2x i/o itp enable latched input/free running pci clock output. itp_enable selects the functionality of the cpu_itp/src output as follows: 1 = cpu_itp output 0 = src out p ut 9pereq3# in real-time input pin that controls pciexclk outputs that are selected through the smbus. 1 = selected outputs are disabled, 0 = selected outputs are enabled. 10 *sel12_48#/12_48mhz_2x i/o latched select input for 12/48mhz output. 1=12mhz, 0=48mhz. 12/48mhz clock out p ut. 11 vdd pwr power su pp l y , nominal 3.3v 12 fsla/usb48_2x i/o 3.3v tolerant input for cpu frequency selection. low voltage threshold inputs, see input electrical characteristics for vil_fs and vih_fs values. / 48.00mhz usb cloc k 13 gnd pwr ground p in. 14 dott_96mhzlr out true clock of low power differential pair for 96.00mhz dot clock. no 50ohm to gnd needed. no rs needed. 15 dotc_96mhzlr out complementary clock of low power differential pair for 96.00mhz dot clock. no 50ohm resistor to gnd needed. no rs needed. 16 fslb in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 17 gndsata pwr ground p in for the sata out p uts 18 satat_lr/pciet_lr3 out true clock of differential sata pair. / true clock of differential pci-express pair - selectable by fs(4:3) ; both are 0.8v differential push pull outputs with inte g rated 33ohm series resistor. 19 satac_lr/pciec_lr3 out complementary clock of differential sata pair. / complementary clock of differential pci-express pair - selectable by fs(4:3); both are 0.8v differential p ush p ull out p uts with inte g rated 33ohm series resistor. 20 vddsata pwr su pp l y for sata clocks, 3.3v nominal 21 pciet_lr0 out true clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 22 pciec_lr0 out complementary clock of 0.8v differential push-pull pci_express pair with inte g rated 33ohm series resistor 23 pciet_lr1 out true clock of 0.8v differential push-pull pci_express pair with integrated 33ohm series resistor 24 pciec_lr1 out complementary clock of 0.8v differential push-pull pci_express pair with inte g rated 33ohm series resistor
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 4 pin description (continued) 25 gnd pwr ground p in. 26 vddpciex pwr power suppl y for pci express clocks, nominal 3.3v 27 cpuitpc_lr2/pciec_lr2 out complementary clock of differential pair cpu output. / complementary clock of differential pciex pair. these are 0.8v push pull outputs. no external 50ohm resistor to gnd or 33ohm series resistor needed. 28 cpuitpt_lr2/pciet_lr2 out true clock of differential pair cpu output. / true clock of differential pciex pair. these are 0.8v push pull outputs. no external 50ohm resistor to gnd or 33ohm series resistor needed. 29 cpuc_lr1 out complementary clock of differential pair 0.8v push-pull cpu outputs with inte g rated 33ohm series resistor. 30 cput_lr1 out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. 31 vddcpu pwr su pp l y for cpu clocks, 3.3v nominal 32 cpuc_lr0 out complementary clock of differential pair 0.8v push-pull cpu outputs with inte g rated 33ohm series resistor. 33 cput_lr0 out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. 34 gnd pwr ground pin. 35 sclk in clock pin of smbus circuitr y , 5v tolerant. 36 sdata i/o data p in for smbus circuitr y , 5v tolerant. 37 cpu_stop# in sto p s cpu0 clock when enabled. 38 pci&pciex_stop# in stops all pciclks at logic 0 level, when low. free running pciclks are not effected b y this in p ut. 39 x2_25 out cr y stal out p ut, nominall y 25.00mhz. 40 x1_25 in cr y stal input, nominall y 25.00mhz. 41 gnd pwr ground p in. 42 25mhz out 25mhz clock out p ut, 3.3v 43 vddsusp pwr supply for suspend mode, powers 25mhz pll, 25m output and xtal oscillator. 3.3v nominal 44 vtt_pwrgd/wol_stop# in this active high 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled / asynchronous active low input pin that stops all outputs except free running 25mhz 45 vdd14 pwr power for 14.31818mhz pll and ref out p ut, nominal 3.3v. 46 ref0_2x/fslc i/o 2x strength 14.318 mhz reference clock./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 47 gnd pwr ground pin. 48 gnd pwr ground p in.
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 5 block diagram general description the ICS9LPRS436C is a low power ck505-compatible clock targeted at intel-based netbooks and nettops. this clock synthesizer provides a single chip solution for systems using the intel nm10 chipset paired with the intel n450/d410/d510 atom ? cpus. the ICS9LPRS436C is driven with a 25mhz crystal. series resistors for single ended outputs 1 load rs= 2 loads rs= 3 loads rs= 1 0.56 / 33 (17 ? )33 ? [39 ? ] - - 2 0.92 / 66 (14 ? )39 ? [43 ? ]22 ? [27 ? ]- notes: 2. desktop/mobile platforms with zo = 50/55 ohms use the first resistor value. 3. systems with zo = 60 ohms use the resistor values in brackets [ ]. match point for n & p voltage / current (ma) 1. preferred drive strengths using ck505 clock sources. transmission lines to load do not share series resistors. number of loads to drive number of loads actually driven. d.c.drive strength nonss pll 25m xtal ss pll nonss pll 48mhz dot96 12_48mhz pci cpu pcie/ sata 12.288m 14.318m nonss pll 75m/ 100m 25m
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 6 table 1: cpu/src/pci pll spread frequency selection table for 9lprs436 c fs4 (b0b4) fs3 (b0b3) fs l c (b0b2) fs l b (b0b1) fs l a (b0b0) cpu mhz src pci sata 0 0 0 0 0 0 100.00 100.00 33.33 follows src 1 0 0 0 0 1 100.00 100.00 33.33 follows src 2 0 0 0 1 0 83.33 100.00 33.33 follows src 3 0 0 0 1 1 83.33 100.00 33.33 follows src 4 0 0 1 0 0 133.33 100.00 33.33 follows src 5 0 0 1 0 1 133.33 100.00 33.33 follows src 6 0 0 1 1 0 166.67 100.00 33.33 follows src 7 00 1 11 166.67 100.00 33.33 follows src 8 0 1 0 0 0 100.00 100.00 33.33 100mhz non-s p read 9 0 1 0 0 1 100.00 100.00 33.33 100mhz non-s p read 10 0 1 0 1 0 83.33 100.00 33.33 100mhz non-s p read 11 0 1 0 1 1 83.33 100.00 33.33 100mhz non-s p read 12 0 1 1 0 0 133.33 100.00 33.33 100mhz non-s p read 13 0 1 1 0 1 133.33 100.00 33.33 100mhz non-s p read 14 0 1 1 1 0 166.67 100.00 33.33 100mhz non-s p read 15 01 1 11 166.67 100.00 33.33 100mhz non-spread 16 1 0 0 0 0 100.00 100.00 33.33 75mhz non-s p read 17 1 0 0 0 1 100.00 100.00 33.33 75mhz non-s p read 18 1 0 0 1 0 83.33 100.00 33.33 75mhz non-s p read 19 1 0 0 1 1 83.33 100.00 33.33 75mhz non-s p read 20 1 0 1 0 0 133.33 100.00 33.33 75mhz non-s p read 21 1 0 1 0 1 133.33 100.00 33.33 75mhz non-s p read 22 1 0 1 1 0 166.67 100.00 33.33 75mhz non-s p read 23 10 1 11 166.67 100.00 33.33 75mhz non-spread 24 1 1 0 0 0 100.00 100.00 33.33 75mhz non-s p read 25 1 1 0 0 1 100.00 100.00 33.33 75mhz non-s p read 26 1 1 0 1 0 83.33 100.00 33.33 75mhz non-s p read 27 1 1 0 1 1 83.33 100.00 33.33 75mhz non-s p read 28 1 1 1 0 0 133.33 100.00 33.33 75mhz non-s p read 29 1 1 1 0 1 133.33 100.00 33.33 75mhz non-s p read 30 1 1 1 1 0 166.67 100.00 33.33 75mhz non-s p read 31 11 1 11 166.67 100.00 33.33 75mhz non-spread
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 7 cpu power management table 1 enable 1 x running running 1 enable 0 xhighlow 0 enable x x low low x dis ab le xxlowlow cpu(1:0)/itp cpu#(1:0)/itp cpu_stop# pci&pciex_ stop# wol_stop# smbus re g is t e r oe differential power management table pciex/sata pciex/sata# pciex/sata pciex/sata# 1 enable x 1 running running running running running running 1 enable x 0 high low running running running running 0 enable x x low low low /20k low low /20k low x dis able x x low low low /20k low low /20k low dot # fr e e - ru n dot cpu_stop# pci&pciex_ stop# sm bus re g is t e r oe pci stoppable wol_stop# singled-ended power management table pcif/pci pcif/pci 25mhz 25mhz free-run stoppable free-run stoppable 1 enable x 1 running running running running running running 1 enable x 0 running low running running running running 0 enable x x low low low low running low x dis able x x low low low low low low 12/48mhz 12.288mhz ref wol_stop# cpu_stop# pci&pciex_ stop# sm bus re g is t e r oe pereq# control table: 10, sata/pcie3 2 sata/pcie3, 1 31, 2 pereq# pcie controlled table 2: slew rate selection table bit 1 bit 0 slew rate 00 hi-z 01 0.6x (1.2v/ns) 10 0.8x (1.6v/ns) 11 1x (2.0v/ns)
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 8 electrical characteristics - absolute maximum ratings parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 case temperature tcase 115 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - input/supply/common output dc parameters parameter symbol conditions min typ max units notes t ambc standard device 0 85 c t amb i industrial temperature range device -40 85 c supply voltage vddxxx supply voltage 3.135 3.465 v input high voltage v ihse single-ended 3.3v inputs 2 v dd + 0.3 v 7 input low voltage v ilse single-ended 3.3v inputs v ss - 0.3 0.8 v 7 fs(4:3) input high voltage v ih_fs4 single-ended 3.3v fs(4:3) inputs 2 vdd + 0.3 v fs(4:3) input low voltage v il_fs4 single-ended 3.3v fs(4:3) inputs v ss - 0.3 0.8 v low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 vdd+0.3 v low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v input leakage current i in v in = v dd , v in = gnd -5 5 ua 6 input leakage current i inres inputs with pull up or pull down resistors v in = v dd , v in = gnd -200 200 ua output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 5 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 5 i ddvdd3. 3 full active, c l = full load; idd 3.3v 100 ma i ddvddsusp3. 3 full active, c l = full load; idd 3.3v 13 ma i ddpdvdd3. 3 3.3v main rail 0 ma i ddpdsusp3. 3w vdd_susp rail. 25mhz running (wol) 13 ma i ddpdsusp3.3 vdd_susp rail. 25mhz off 2 ma input frequency f i v dd = 3.3 v 27 mhz 8 pin inductance l p in 7nh c in logic inputs 1.5 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 6 pf smbus voltage v dd 2.7 5.5 v low-level output voltage v olsmb @ i pullup 0.4 v current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma sclk/sdata clock/data rise time t ri 2c (max vil - 0.15) to (min vih + 0.15) 1000 ns sclk/sdata clock/data fall time t fi 2c (min vih + 0.15) to (max vil - 0.15) 300 ns maximum smbus operating frequency f smbus 100 khz spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 operation at these points is not recommended 4 operation under these conditions is neither implied, nor guaranteed. 5 signal is required to be monotonic in this region. 6 input leakage current does not include inputs with pull-up or pull-down resistors 2 maximum vih is not to exceed vdd 3 human body model 8 for margining purposes only. normal operation should have fin = 25mhz +/-50ppm 7 3.3v referenced inputs are: pci&pciex_stop#, cpu_stop#, itp_en, sclk, sdata, vtt_pwr_gd/pd#, sel12_48# and pereq# inputs if sel ected. notes on dc parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). ambient operating temp operating supply current powerdown current input capacitance
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 9 ac electrical characteristics - input/common parameters parameter symbol conditions min typ max units notes clk stabilization t stab from vdd power-up or de-assertion of pd to 1st clock 1.8 ms tdrive_pereq_off t drperoff output stop after pereq# deasserted 3 clocks tdrive_pereq_on t drperon output run after pereq# asserted 3 clocks tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 10 ns tdrive_pciex t drpci ex pciex output enable after pci&pciex_stop# de-assertion 15 ns 1 tfall_se t fall 10 ns trise_se t ri se 10 ns tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 fall/rise time of all 3.3v control inputs from 20-80% ac electrical characteristics - cpu, pciex, sata, dot96mhz parameter symbol conditions min typ max units notes rising edge slew rate tslr differential measurement 2.5 4 v/ns 1,2 falling edge slew rate tflr differential measurement 2.5 4 v/ns 1,2 slew rate variation tslvar single-ended measurement 20 % 1 maximum output voltage vhigh includes overshoot 1150 mv 1 minimum output voltage vlow includes undershoot -300 mv 1 differential voltage swing vswing differential measurement 300 mv 1 crossing point voltage vxabs single- ended measurement 300 550 mv 1,3,4 crossing point variation vxabsvar single- ended measurement 140 mv 1,3,5 duty cycle dcyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpujc2c differential measurement 85 ps 1 src jitter - cycle to cycle srcjc2c differential measurement 125 ps 1 sata jitter - cycle to cycle satajc2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotjc2c differential measurement 250 ps 1 cpu[1:0] skew cpuskew10 differential measurement 100 ps 1,6 cpu[2_itp:0] skew cpuskew20 differential measurement 150 ps 1,6 src skew srcskew differential measurement 250 ps 1 electrical characteristics - pciclk/pciclk_f parameter symbol conditions min typ max units notes output impedance r dsp v o = v dd *(0.5) 12 55 ? 1 long accuracy ppm see tperiod min-max values -100 100 ppm 2 33.33mhz output no spread 29.99700 30.00300 ns 2 33.33mhz output spread 30.08421 30.23459 ns 2 33.33mhz output no spread 29.49700 30.50300 ns 2 33.33mhz output nominal/spread 29.56617 30.58421 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t sl r measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t fl r measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 pin to pin skew t ske w v t = 1.5 v 250 ps 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =5pf, rs=22 ? (unless specified otherwise) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 3 slew rate emastured through v_swing voltage range centered about differential zero 4 vcross is defined at the voltage where clock = clock#. 6 cpu group skew is nominally 0ps. 5 only applies to the differential rising edge (clock rising, clock# falling.) i oh output high current t abs t period clock period absolute min/max period output low current i ol
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 10 electrical characteristics - usb48mhz, 12/48mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 48.00mhz output nominal 20.83125 20.83542 ns 2,3 absolute min/max period t abs 48.00mhz output nominal 20.48125 21.18542 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 rising edge slew rate (usb48m) t sl r measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate (usb48m) t fl r measured from 2.0 to 0.8 v 1 2 v/ns 1 rising edge slew rate (12/48m) t sl r measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate (12/48m) t fl r measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 350 ps 1 electrical characteristics - 25mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 25.00mhz output nominal 39.99600 40.00400 ns 2,3 absolute min/max period t abs 25.00mhz output nominal 39.32360 40.67640 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 rising edge slew rate t sl r measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t fl r measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 electrical characteristics - 12.288mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 12.288mhz output nominal 81.37207 81.38835 ns 2,3 absolute min/max period t abs 12.288mhz output nominal 80.87207 81.88835 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 rising edge slew rate t sl r measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t fl r measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 electrical characteristics - ref-14.318mhz parameter symbo l conditions min typ max units notes lon g accurac y pp m see t p eriod min-max values -100 100 pp m1,2 clock p eriod t p eriod 14.318mhz out p ut nominal 69.82033 69.86224 ns 2,3 absolute min/max p eriod tabs 14.318mhz out p ut nominal 69.83400 70.84800 ns 2 output high voltage voh ioh = -1 ma 2.4 v 1 output low voltage vol iol = 1 ma 0.4 v 1 rising edge slew rate tslr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate tflr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle dt1 vt = 1.5 v 45 55 % 1 jitter, c y cle to c y cle t j c y c-c y c vt = 1.5 v 1000 p s1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =5pf, rs=22 ? (unless specified otherwise) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 3 the average period over any 1us period of time
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 11 lvds clk input l4 l4? r8b r7b r8a r7a 3.3 volts 9lprs436 cc cc driving lvds inputs with the 9lprs436 receiver has termination receiver does not have termination r7a, r7b 10k ohm 140 ohm r8a, r8b 5.6k ohm 75 ohm cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts component note value
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 12 general smbus serial interface information for the ICS9LPRS436C how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the beginning byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 13 smbus table: frequency select register byte 0 name control function type 0 1 pwd bit 7 reserved 0 bit 6 reserved 0 bit 5 spread enable enables spread for cpu/src/pci outputs rw off 0.5% down spread 0 bit 4 fs4 freq select bit 4 rw latch bit 3 fs3 freq select bit 3 rw latch bit 2 fslc freq select bit 2 rw latch bit 1 fslb freq select bit 1 rw latch bit 0 fsla freq select bit 0 rw latch smbus table: output control register byte 1 name control function type 0 1 pwd bit 7 dot96mhz output enable rw disable enable 1 bit 6 sata/pcie3 output enable rw disable enable 1 bit 5 itp/pcie2 output enable rw disable enable 1 bit 4 pcie1 output enable rw disable enable 1 bit 3 pcie0 output enable rw disable enable 1 bit 2 12.288mhz output enable (disabling this output also disables the 12.288m pll). rw disable enable 1 bit 1 25mhz 25mhz free running during vdd suspend (s-states). if this bit is set to 0, the xtal osc will also be powered down in the suspend states) rw does not run runs 1 bit 0 cpu pll mn_en cpu pll m/n enable rw disable enable 0 smbus table: output control register byte 2 name control function type 0 1 pwd bit 7 usb_48mhz output enable rw disable enable 1 bit 6 0 bit 5 ref0 output enable rw disable enable 1 bit 4 25mhz output enable rw disable enable 1 bit 3 12_48mhz output enable rw disable enable 1 bit 2 pciclk_f0 output enable rw disable enable 1 bit 1 pciclk0 output enable rw disable enable 1 bit 0 0 smbus table: output control register byte 3 name control function type 0 1 pwd bit 7 cpuclk1 output enable rw disable enable 1 bit 6 cpuclk0 output enable rw disable enable 1 bit 5 pereq3# control pciex1 is controlled rw not controlled controlled 0 bit 4 pereq3# control pciex2 is controlled rw not controlled controlled 0 bit 3 pereq2# control pciex1 is controlled rw not controlled controlled 0 bit 2 pereq2# control sataclk is controlled rw not controlled controlled 0 bit 1 pereq1# control pciex0 is controlled rw not controlled controlled 0 bit 0 pereq1# control sataclk is controlled rw not controlled controlled 0 note: only 1 pereq at a time can be selected to control an output. reserved reserved see table 1: cpu/src/pci pll frequency selection table
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 14 smbus table: output control and readback register byte 4 name control function 0 1 pwd bit 7 0 bit 6 cpu_1 free-running control rw free-running stoppable 0 bit 5 sel_12_48 sel12_48mhz readback r 48mhz 12mhz latch bit 4 cpuclk_2/itp free-running control rw free-running stoppable 0 bit 3 itp_en itp_en readback r pciex6 cpu_itp latch bit 2 0 bit 1 cpuclk_0 free-running control rw free-running stoppable 0 bit 0 0 smbus table: output control register byte 5 name control function 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 sata/pcie3 free- running control rw free-running stoppable 1 bit 3 pcie2 free- running control rw free-running stoppable 0 bit 2 pcie1 free- running control rw free-running stoppable 0 bit 1 pcie0 free- running control rw free-running stoppable 0 bit 0 load control iic load control rw load do not load 0 smbus table: amplitude control register byte 6 name control function type 0 1 pwd bit 7 diff amp rw 00 = 700mv 10 = 900mv 0 bit 6 diff amp rw 01 = 800mv 11 = 1000mv 1 bit 5 diff amp rw 00 = 700mv 10 = 900mv 0 bit 4 diff amp rw 01 = 800mv 11 = 1000mv 1 bit 3 diff amp rw 00 = 700mv 10 = 900mv 0 bit 2 diff amp rw 01 = 800mv 11 = 1000mv 1 bit 1 diff amp rw 00 = 700mv 10 = 900mv 0 bit 0 diff amp rw 01 = 800mv 11 = 1000mv 1 smbus table: revision and vendor id register byte 7 name control function type 0 1 pwd bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 0010 = c rev vendor id sata/pcie3 differential output amplitude control dot96 differential output amplitude control reserved reserved reserved revision id 0001 = ics cpu differential output amplitude control reserved reserved reserved pcie(2:0) differential output amplitude control
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 15 smbus table: byte count register byte 8 name control function type 0 1 pwd bit 7 reserved 0 bit 6 reserved 0 bit 5 reserved 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 1 bit 1 bc1 rw 1 bit 0 bc0 rw 1 smbus table: watch dog timer control register byte 9 name control function type 0 1 pwd bit 7 hwd_en watchdog hard alarm enable rw disable enable 0 bit 6 wd hard status wd hard alarm status r normal alarm x bit 5 wdtctrl watch dog alarm time base control r0 bit 4 hwd3 wd hard alarm timer bit 3 rw 1 bit 3 hwd2 wd hard alarm timer bit 2 rw 1 bit 2 hwd1 wd hard alarm timer bit 1 rw 1 bit 1 hwd0 wd hard alarm timer bit 0 rw 1 bit 0 reserved reserved rw - - 0 smbus table: skew programming register byte 10 name control function type 0 1 pwd bit 7 cpuskw3 rw 0 bit 6 cpuskw2 rw 0 bit 5 cpuskw1 rw 0 bit 4 cpuskw0 rw 0 bit 3 cpuskw3 rw 0 bit 2 cpuskw2 rw 0 bit 1 cpuskw1 rw 0 bit 0 cpuskw0 rw 0 cpu skew programming table byte 10 bits [7:4] or bits [3:0] skew value (ps) 0000 0 0001 100 0010 200 0011 300 0100 400 0101 500 0110 600 0111 700 1000 800 1001 900 1010 1000 1011 1100 1100 1200 1101 1300 1110 1400 1111 1500 290ms base cpuclk0 skew control (ps) writing to this register will configure how many bytes will be read back, default is 0f = 15 bytes. byte count programming these bits represent x*290ms or x*1.16s. the watchdog timer waits before it goes to alarm mode. default is 15 x 290ms = 4.35s. cpuclk1 skew control (ps) see cpu skew programming table see cpu skew programming table
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 16 smbus table: cpu/src/pci pll frequency control register byte 11 name control function type 0 1 pwd bit 7 n div2 n divider prog bit 2 rw x bit 6 n div1 n divider prog bit 1 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x smbus table: cpu/src/pci pll frequency control register byte 12 name control function type 0 1 pwd bit 7 n div10 rw x bit 6 n div9 rw x bit 5 n div8 rw x bit 4 n div7 rw x bit 3 n div6 rw x bit 2 n div5 rw x bit 1 n div4 rw x bit 0 n div3 rw x smbus table: cpu/src/pci pll frequency control register byte 13 name control function type 0 1 pwd bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x smbus table: cpu/src/pci pll frequency control register byte 14 name control function type 0 1 pwd bit 7 ssp15 rw 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x bytes [15:22] are reserved spread spectrum programming bit(15:8) spread spectrum programming bit(7:0) n divider programming byte12 bit(7:0) and byte11 bit(7:6) m divider programming bit (5:0) these spread spectrum bits in byte 13 and 14 w ill program the spr ead percentage of cpu pll these spread spectrum bits in byte 13 and 14 w ill program the spr ead percentage of cpu pll the decimal representation of m and n divider in byte 11 and 12 will configure the cpu pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 50 x ndiv(10:0)/mdiv(5:0) the decimal representation of m and n divider in byte 11 and 12 will configure the cpu pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 50 x ndiv(10:0)/mdiv(5:0)
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 17 smbus table: se slew rate control register byte 23 name control function type 0 1 pwd bit 7 rw 00 = hi-z 01 = 0.6x (1.2v/ns) 1 bit 6 rw 10 = 0.8x (1.6v/ns) 11 = 1x (2.0v/ns) 0 bit 5 rw 00 = hi-z 01 = 0.6x (1.2v/ns) 1 bit 4 rw 10 = 0.8x (1.6v/ns) 11 = 1x (2.0v/ns) 0 bit 3 rw 00 = hi-z 01 = 0.6x (1.2v/ns) 1 bit 2 rw 10 = 0.8x (1.6v/ns) 11 = 1x (2.0v/ns) 0 bit 1 rw 00 = hi-z 01 = 0.6x (1.2v/ns) 1 bit 0 rw 10 = 0.8x (1.6v/ns) 11 = 1x (2.0v/ns) 0 byte [24] is reserved smbus table: se outputcontrol register byte 25 name control function type 0 1 pwd bit 7 rw 00 = really hi-z 01 = 0.6x (1.2v/ns) 1 bit 6 rw 10 = 0.8x (1.6v/ns) 11 = 1x (2.0v/ns) 0 bit 5 pciclk_f0 free- running control rw free-running stoppable 0 bit 4 pciclk0 free- running control rw free-running stoppable 1 bit 3 rw 00 = really hi-z 01 = 0.6x (1.2v/ns) 1 bit 2 rw 10 = 0.8x (1.6v/ns) 11 = 1x (2.0v/ns) 0 bit 1 rw 00 = really hi-z 01 = 0.6x (1.2v/ns) 1 bit 0 rw 10 = 0.8x (1.6v/ns) 11 = 1x (2.0v/ns) 0 byte [26:30] are reserved 12_48m slew ref slew 48m slew pciclk_f0 slew pciclk0 slew 12.288m slew 25m slew slew rate control slew rate control slew rate control slew rate control slew rate control slew rate control slew rate control
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 18 48-pin mlf package drawing and dimensions dimensions a0.81.0 n 48 a1 0 0.05 n d 12 a3 n e 12 b 0.18 0.3 d x e basic 6.00 x 6.00 e d2 min. / max. 3.95 / 4.25 e2 min. / max. 3.95 / 4.25 l min. / max. 0.30 / 0.50 0.20 reference 0.40 basic 48l tolerance thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions symbol min. max. symbol top view index area d sawn singulation anvil singulation a 0. 08 c c a3 a1 seating plane e2 e2 2 l (n -1)x e (ref.) & n n even n e d2 2 d2 (re f.) & odd 1 2 e 2 (typ.) (ref.) (ref.) if n & n (n -1)x b thermal base n or chamfer 4x 0.6 x 0.6 max optional e d n n d d d are even
idt ? low power clock for intel atom ? -based systems 1561a ? 06/01/10 ICS9LPRS436C low power clock for intel atom ? -based systems 19 min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10 - 0 0 3 9 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) ref er ence do c.: jedec pub licat io n 9 5, m o- 153 index a rea 12 n d e1 e seating plane a1 a a2 e - c - b c l aaa c 48-pin tssop package drawing and dimensions ordering information part / order number shipping package package temperature 9lprs436cklf tubes 48-pin mlf 0 to +85 c 9lprs436cklft tape and reel 48-pin mlf 0 to +85 c 9lprs436ckilf tubes 48-pin mlf -40 to +85 c 9lprs436ckilft tape and reel 48-pin mlf -40 to +85 c 9lprs436cglf tubes 48-pin tssop 0 to +85 c 9lprs436cglft tape and reel 48-pin tssop 0 to +85 c 9lprs436cgilf tubes 48-pin tssop -40 to +85 c 9lprs436cgilft tape and reel 48-pin tssop -40 to +85 c ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. "c" is the revision designator (will not correlate to the datasheet revision)
ICS9LPRS436C low power clock for intel atom ? -based systems 20 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issue date requestor description page # 0.1 12/14/2009 rdw initial release of c rev with updated frequency select table and updated idd specs for suspend state. 48 mlf pinout also added. - 0.2 12/18/2009 rdw corrected iddpdvdd3.3 parameter to be 0 ma 0.3 1/18/2010 rdw updated block diagram 5 0.4 6/1/2010 rdw corrected smbus as follows: 1. byte0, bits (4:0) are read/write not read only 2. byte 6 is as follows: b(7:6) control pcie(2:0), b(5:4) control dot96, b(3:2) control pcie3/sata, b(1:0) control cpu. 3. added '0010 = c rev' to byte 7 description for c rev. 4. updated absolute max ratings to indicate max smbus vhigh is 5.5v. 5. removed ioh and iol specifications from single ended output electrical characteristics tables. these values are indirectly determined by the output termination table. 6. typical column added to electrical characteristics tables. 7. general description updated. 8. references to i2c clarified to refer to smbus 9. minor formattin g updated to smbus b y tes 23, and 25. 5, 8-11, 13,14 a 6/1/2010 rdw released to final

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